40.4.4 Pause Frame Support

The following table summarizes the start of an 802.3 pause frame.

The EMAC_NCFGR contains a receive ‘Pause Enable’ bit (13). If a valid pause frame is received, the Pause Time Register (EMAC_PTR) is updated with the frame’s pause time, regardless of its current contents and regardless of the state of the EMAC_NCFGR bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the Interrupt Mask Register (EMAC_IMR). If bit 13 is set in the EMAC_NCFGR and the value of the EMAC_PTR is non-zero, no new frame is transmitted until the EMAC_PTR has decremented to zero.

The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is still triggered.

A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frames Received Register (EMAC_PFR).

The EMAC_PTR decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. For test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (‘Retry Test’) is set in the EMAC_NCFGR. If the ‘Pause Enable’ bit (13) is not set in the EMAC_NCFGR, then the decrementing occurs regardless of whether transmission has stopped or not.

An interrupt (13) is asserted whenever the EMAC_PTR decrements to zero (assuming it is enabled in the EMAC_IMR).