58.6.2.4 Flexible Serial Communication Controller (FLEXCOM) - TWI

The TWI communicates in Standard, Fast, Fast Mode Plus and High-Speed (HS) modes subject to the following:
  • When the registers FLEX_TWI_CWGR, FLEX_TWI_HSCWGR and FLEX_TWI_MMR are programmed in the TWI Controller
  • When pull-ups (Rp) are computed to achieve the required rise time according to the total Cbus capacitance.

Possible limitations are given in the table and figures below.

Table 58-24. Two-Wire Interface I/O Characteristics
Symbol Parameter Conditions Min Max Unit
VIL , VIH Low-level/High-level Input Voltage

All modes

 See note (1) V
VOL , VOH Low-level/High-level Output Voltage

All modes

 See note (2) V
IOL Low-level Output Current

Standard

Fast

Fast-Mode Plus

See notes (2, 3) mA
High-speed Mode See note (2)

tf

Output fall time of both TWD and TWCK signals VIHmin to VILmax

Standard

Fast

Fast-Mode Plus

See note (4) ns

tfTWCK, tfTWD

Fall time of both TWD and TWCK signals

High-speed Mode
trTWCK Rise time of TWCK, rise boost mode (push-pull mode) SCLRBL > 0 See note (5) ns
Note:
  1. See the table Input DC Characteristics.
  2. See the tables Output DC Characteristics (1.7V < VDD < 1.9V) and Output DC Characteristics (3.0V < VDD < 3.6V). If Rp(min) as specified in the I2C specification must be overridden (stronger) to meet the timing specification, the IBIS model of the product can be used to extract VOL(max) vs IOL.
  3. 20 mA is not supported for Fast Mode Plus.
  4. Fall time of FLEXCOM I/O buffers are not I2C-compliant. Fall time can be increased by adding series resistors (see series protection resistors in the I2C specification). Rs < 1 KΩ depending on Cbus and Rp to respect VOL, VIL on the bus. Use Drive disabled (set to 0) and Slew rate enabled (set to 1) on the corresponding I/O. In the I/O AC Characteristics section, see falling times given for a 10 pF load. IBIS models of the product can be used to choose an adequate Rs value by simulating different drive/slew rate combinations with respect to the Cbus load.
  5. When in High-speed mode, the TWI Clock signal (TWCK) rise can be boosted to meet a very fast rise time of the parameter trCL of the I2C specification when the Rp value on TWCK is lower than Rp(min).
    Bits in FLEX_TWI_MMR.SCLRBL must be programmed according to tMCKx to respect these timings. This gives the number of peripheral clock periods during which the SCL rise is boosted, i.e. driven in Push-pull mode. Note that the Cbus value and the drive and slew rate settings still influence the rise time. Rise boost usage is more suited with high Cbus values.
    Note: MCKx refers to the MCK associated with the FLEXCOM. Refer to the Domain Clock column in the table “Peripheral Identifiers”.
Figure 58-17. TWCK High-Speed Mode with Rise Boost Enabled

The figure below shows programmable register fields (CLDIV/HSCLDIV, CHDIV/HSCHDIV and optional CKDIV/HSCKDIV) in relation to tLOW, tHIGH , tr, tf, fSCL, trCL, trCL1, tfCL from the I2C specification.

Figure 58-18. TWCK Timings Characteristics
Note: Symbols with an asterisk (*) are I2C specification symbols: tLOW, tHIGH, tr , tf.
Note: For High-speed mode, tr = trCL or trCL1 and tf = tfCL from the I2C specification.
Important: tSCL ≅ tLOW(min) + tr(max)+ tHIGH(min) + tf(max)