62.4 DS60001579D - 09/2020
Section | Changes |
---|---|
Added automotive content in Features, Electrical Characteristics, Ordering Information and Product Identification System | |
Reset Controller (RSTC) |
Added NRST_OUT content |
Debug Unit (DBGU) |
Updated ICE Access Prevention |
Slow Clock Controller (SCKC) |
Updated Embedded Characteristics |
Power Management Controller (PMC) |
Updated General Clock Distribution Block Diagram PMC_PLL_UPDT: corrected STUPTIM field size |
DMA Controller (XDMAC) |
Transfer Hierarchy Diagrams: removed "XDMAC Peripheral Transfer Hierarchy" figure Added Peripheral to Memory Transfer and Memory to Peripheral Transfer |
LCD Controller (LCDC) |
Embedded Characteristics: updated Output mode content Updated YUV Frame Buffer Memory Mapping Renamed and updated Window Size table |
2D Graphics Engine (GFX2D) |
BLEND_WD0: added DREG field BLEND_WD5: replaced DFACT and SFACT by DCFACT and SCFACT, respectively; added DPRE, DAFACT, SPRE and SAFACT fields GFX2D_GC: removed bits CGDISCORE, CGDISAXI, CGDISFIFO |
USB Host High Speed Port (UHPHS) |
Corrected reset values for:
|
Image Sensor Interface (ISI) |
Added write-protection content ISI_CFG2: updated RGB_SWAP and RGB_CFG bit descriptions ISI_Y2R_SET1: updated Yoff, Croff and Cboff bit descriptions ISI_R2Y_SET0: updated Roff bit description ISI_R2Y_SET1: updated Goff bit description ISI_R2Y_SET2: updated Boff bit description |
Timer Counter (TC) | Updated Removed unrequired fault output content |
Triple Data Encryption Standard (TDES) |
Updated TDES_MR |
Electrical Characteristics |
Updated Table 58-60 (CPU clock (HCLK) row) |