62.6 DS60001579B - 02/2020

Section Changes
All sections Changed order of bits (now from MSB to LSB) in Register Summary tables
Safety and Security Features Removed "Classical Advanced Software Crypto Library (CASCL)" from Security Features table
Peripherals

Updated FLEXCOM Features table

Boot Strategies Updated NAND Flash Boot: NAND Flash Detection introduction
OTP Memory Controller (OTPC)

OTPC_CR: updated READ bit description

Clock Generator Updated Main Clock (MAINCK) Block Diagram
Power Management Controller (PMC)
Updated:
PMC_CPU_CKR: corrected MDIV field width
External Bus Interface (EBI)

Updated Multi-Port DDR and SDRAM Controllers

AHB Multiport DDR-SDRAM Controller (MPDDRC)

DDR2-SDRAM Initialization: added TRFC constraint content

Monitor: added monitor use example

Flexible Serial Communication Controller (FLEXCOM)

Added introduction in USART FIFO Mode Register. USART FIFO Level Register, USART FIFO Interrupt Mask Register, SPI Status Register, SPI FIFO Mode Register, SPI FIFO Level Register, TWI FIFO Mode Register, TWI FIFO Level Register, TWI FIFO Status Register and TWI FIFO Interrupt Mask Register.

Image Sensor Interface (ISI)

Power Management: added note

Timer Counter (TC)

Embedded Characteristics: corrected number of channels

Block Diagram: added Note 2

TC_SRx: corrected SECE bit position

Advanced Encryption Standard (AES)
Updated:
Secure Hash Algorithm (SHA)

SHA_MR: updated ALGO bit field description

True Random Number Generator (TRNG)

TRNG_PKBCR: updated KSLAVE field description

Electrical Characteristics
Mechanical Characteristics

Updated 228-ball TFBGA Mechanical Characteristics

Marking Updated Line 4 description