| Global | Editorial changes throughout |
| Reference Document | Added. |
| Memories | DDR/SDR I/O Calibration: updated memory types for
resistor values. |
| General Purpose Backup Registers (GPBR) |
GPBR_FCLR: updated register description.
|
| Watchdog Timer (WDT) |
WDT_MR: corrected positions of bits WDDBGHLT and WDIDLEHLT.
|
| Reset Controller (RSTC) |
RSTC_SR: updated reset value.
|
| Real-Time Timer (RTT) |
RTT Counting: updated.
RTT_TSR: added TS_OVF bit; increased TSTAMP field width.
|
| Real-Time Clock (RTC) |
RTC
Accurate Clock Calibration: updated.
Waveform Generation: updated.
Waveform Generation for ADC Trigger Event:
updated.
RTC_MR: index 1 now ‘reserved’. Bit UTC, index 2, updated.
RTC_SR: updated reset value.
Added (DEFAULT_MODE) to register names: |
| OTP Memory Controller (OTPC) |
Power
Management: updated.
|
| Bus Matrix (MATRIX) |
No
Default Host: updated.
Slot
Cycle Limit Arbitration: updated.
|
| Slow Clock Controller (SCKC) |
Switching from Embedded 32 RC Oscillator to 32.768 kHz Crystal
Oscillator: modified from 4 to 39000 the number of slow clock
cycles to wait for internal resynchronization
|
| Power Management Controller (PMC) |
32.768
kHz Crystal Oscillator: removed “Reverting to the slow RC
oscillator is only possible by shutting down the VDD_NAME power supply.”
Main
Crystal Oscillator Failure Detection: updated.
CKGR_MOR: corrected reset value.
|
| DMA Controller (XDMAC) | Memory to Peripheral Transfer Hierarchy:
updated. |
| USB Device High Speed Port (UDPHS) |
Transfer Without DMA: modified code content.
Added (DEFAULT_MODE) to register names:
|
| Inter-IC Sound Multi-Channel Controller (I2SMCC) |
I2S
Reception and Transmission Sequence: updated text, figures and
tables.
Left-Justified Reception and Transmission Sequence: updated.
I2SMCC_MRB: DMACHUNK description updated. I2SLINESIZE description
updated for values 1 and 2.
I2SMCC_ISRA: RXLRDYx and TXRRDYx bit descriptions updated.
|
| Flexible Serial Communication Controller (FLEXCOM) |
I/O
Lines Description: updated.
Baud
Rate in Synchronous Mode: updated.
Bus
Clear Command, FIFO
Pointer Error, FLEX_TWI_CR: modified.
FLEX_TWI_SR (DEFAULT_MODE): updated reset value.
|
| Quad Serial Peripheral Interface (QSPI) |
QSPI
Bus Clock Modes: updated.
|
| Secure Digital MultiMedia Card Controller (SDMMC) |
SDMMC_CA0R: deleted note (2). Updated bit descriptions with
standard “read-only” mention.
SDMMC_CA1R: updated reset value.
|
| Image Sensor Interface (ISI) |
VSYNC/HSYNC Data Timing: updated.
|
| Timer Counter (TC) |
Block
Diagram: updated.
TC_BMR: updated TCxXCxS descriptions.
|
| Triple Data Encryption Standard (TDES) |
TDES_MR: updated reset value
|
| Random Number Generator (TRNG) |
TRNG_WPSR: modified SWETYP description (value 5).
|
| Analog-to-Digital Controller (ADC) |
ADC_MR: updated reset value.
ADC_PDR: corrected number of channels.
|
| Electrical Characteristics |
I/O
Characteristics: Table 58-13 and Table 58-14: updated with VOL and VOH
values.
FLEXCOM
TWI Characteristics: updated text and figures.
EMAC
Timings: updated EMAC 2 min value.
Low-Power Modes Summary: updated.
|
