| Global |
Editorial changes throughout |
| 11 Debug and Test |
Updated IEEE 1149.1 JTAG Boundary Scan, JTAG ID Code value in JTAG ID
Code Register
|
| 12 Boot Strategies |
Added Secure Boot Strategy section
Updated Default Boot Sequence (Without Boot Configuration Packet)
|
| 13 System Controller Write Protection
(SYSCWP) |
Corrected System
Controller Peripheral Mapping |
| 14 General Purpose Backup Registers (GPBR) |
Corrected GPBRRPx and GPBRWPx field widths in GPBR_MR
|
| 16 Reset Controller (RSTC) |
Updated Block Diagram, Figure 16-6, EXTRST description in RSTC_CR
|
| 18 Real-Time Clock (RTC) |
Updated RTC_CR, RTC_MR, RTC_TIMALR, RTC_CALALR, RTC_CALALR
(UTC_MODE)
|
| 23 OTP Memory Controller (OTPC) |
Added Product Dependencies section
|
| 28 Clock Generator |
Corrected formula in Divider and Phase Lock
Loop Programming
|
| 29 Power Management Controller (PMC) |
Updated ID description in PMC_PLL_UPDT, WIP
description in PMC_WCR, PID
description in PMC_PCR
Removed references to MAINXTALCK in General Clock Distribution Block Diagram, USB Clock
Controller, PMC_USB
|
| 32 DDR-SDRAM Controller (MPDDRC) |
Removed the term “multiport” throughout
Added Interrupt Sources section
Updated Bus Monitor, Performance Monitor, CK_F_RANGE definition in MPDDRC_IO_CALIBR
|
| 33 SDRAM Controller (SDRAMC) |
Updated SDRAM Device Initialization Step 5
Removed references to memory barrier in SDRAM
Device Initialization
|
| 35 Programmable Multibit Error Correction Code Controller (PMECC) |
Updated PMECC_ECCx reset value
|
| 37 DMA Controller (XDMAC) |
Updated Description, and memory-to-memory transfer information in XDMAC
Transfer Software Operation, XDMAC Software
Requirements, XDMAC_CC
|
| 39 2D Graphics Engine (GFX2D) |
Updated Description, Embedded
Characteristics, Block Diagram,
Functional Description, Traffic Balancing Using
Outstanding Regulation
Added field WFEMODE in WFE_WD0
|
| 40 Ethernet MAC 10/100 (EMAC) |
Updated Block Diagram
|
| 41 USB Device High Speed Port (UDPHS) |
Changed “AHB” to “system bus” throughout
Corrected number of end points in UDPHS_IEN, UDPHS_INTSTA, UDPHS_EPTRST
Removed DMA_7 in UDPHS_IEN, UDPHS_INTSTA
Updated Block Diagram, EN_UDPHS description in UDPHS_CTRL
|
| 43 Audio Class D Amplifier (CLASSD) |
Updated Description |
| 44 Inter-IC Sound Multi-Channel Controller (I2SMCC) |
Added Pad Hysteresis Control, note in Host, Controller and
Client Modes, note in Product
Dependencies
Updated TDM Reception and Transmission Sequence, Figure 44-7, I2SMCC_SR, I2SMCC_ISRA and I2SMCC_MRB reset
values
Removed CLKSEL in I2SMCC_MRB
|
| 45 Synchronous Serial Controller (SSC) |
Updated Serial Clock Ratio Considerations
|
| 46 Flexible Serial Communication Controller (FLEXCOM) |
Updates throughout, including addition of sections Digital
Filter and Local Loopback Test Mode
|
| 47 Quad Serial Peripheral Interface (QSPI) |
Updated Block Diagram, Serial Clock
Phase and Polarity, QSPI Bus Clock
Modes, SMRM description in QSPI_MR, CPHA and
CPOL descriptions in QSPI_SCR
|
| 48 Secure Digital MultiMedia Card Controller (SDMMC) |
Added Note 2 in SDMMC_CA0R
Modified SDMMC_PSR reset
value
|
| 51 Timer Counter (TC) |
Updated Table 51-2, Clock Selection, Figure 51-5, Trigger Events, Figure 51-7, Pin
List, TRIGSRCB description in TC_EMR
|
| 52 Pulse Width Modulation Controller (PWM) |
Corrected internal counter size from 32 to 16 bits
Updated Figure 52-1, Figure 52-2, Figure 52-3, DIVA and DIVB descriptions in PWM_MR
|
| 53 Advanced Encryption Standard (AES) |
Updated NIST specifications in Description and
Embedded Characteristics; updated Secure Protocol Layers
Improved Performances, BPE description in AES_EMR, AES_MR reset value
Added PKRPVS content in AES_WPSR and
AES_WPMR
Reinstated missing START bit at index 0 in AES_CR
|
| 54 Secure Hash Algorithm (SHA) |
Throughout: updated FIPS specification reference
Updated Description, Embedded
Characteristics, Internal
Registers for Initial Hash Value or Expected Hash Result, Manual
Mode (steps 4 and 8), ALGO description in SHA_MR, FIRST description in SHA_CR, IDATA description in SHA_IDATARx
Added notes in Automatic Padding, SHA_MSR and DMA
Mode
|
| 55 Triple Data Encryption Standard (TDES) |
Updated PKWO description in TDES_MR
|
| 56 Random Number Generator (TRNG) |
Added sections First Value Read after
Power-up and Entropy
Updated Block Diagram, Functional
Description, HALFR description in TRNG_MR, KSLAVE
description in TRNG_PKCBR
|
| 57 Analog-to-Digital Controller (ADC) |
Updated Figure 57-1, ADC_ACR reset value, TRGSEL description in ADC_MR
|
| 58 Electrical Characteristics |
Reworked Maximum QSPI Frequency
Updated formulas in 32.768 kHz Crystal
Oscillator and Main Crystal
Oscillator
Corrected CPARA32K typical value in Table 58-44
Corrected EMAC3 values in Table 58-35
|
