39.5.1 GFX2D Global Configuration Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					REGQOS3[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	1	1	0


Bit	15	14	13	12	11	10	9	8
	REGQOS2[3:0]				REGQOS1[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	1	0	1	0	0


Bit	7	6	5	4	3	2	1	0
		MTY		REGEN
Access		R/W		R/W
Reset		0		0

Bits 19:16 – REGQOS3[3:0] Regulation for QoS Level 3

This register indicates the number of clock cycles inserted between outstanding transactions. The number of clock cycles added is calculated as follows.

Latency = 2^{REGQOS 3} - 1

The maximum number of clock cycles is 1023.

Bits 15:12 – REGQOS2[3:0] Regulation for QoS Level 2

This register indicates the number of clock cycles inserted between outstanding transactions. The number of clock cycles added is calculated as follows.

Latency = 2^{REGQOS 2} - 1

The maximum number of clock cycles is 1023.

Bits 11:8 – REGQOS1[3:0] Regulation for QoS Level 1

This register indicates the number of clock cycles inserted between outstanding transactions. The number of clock cycles added is calculated as follows.

Latency = 2^{REGQOS 1} - 1

The maximum number of clock cycles is 1023.

Bit 6 – MTY Memory Tile Access

Value	Description
0	GFX2D uses tile accesses.
1	GFX2D uses linear accesses.

Bit 4 – REGEN Outstanding Regulation Enable

Value	Description
0	Outstanding Regulation is disabled.
1	Outstanding Regulation is enabled.

Name:	GFX2D_GC
Offset:	0x00
Reset:	0x00065400
Property:	Read/Write