39.5.9 GFX2D Performance Configuration 0 Register
Name: | GFX2D_PC0 |
Offset: | 0x20 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FILT[2:0] | SEL[1:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bits 6:4 – FILT[2:0] Filter Configuration
Value | Name | Description |
---|---|---|
0 | DISABLED | The filter is disabled. |
1 | QOS0 | Events are valid when input QoS is equal to 0. |
2 | QOS1 | Events are valid when input QoS is equal to 1. |
3 | QOS2 | Events are valid when input QoS is equal to 2. |
4 | QOS3 | Events are valid when input QoS is equal to 3. |
Bits 1:0 – SEL[1:0] Performance Metrics Selection
Value | Name | Description |
---|---|---|
0 | DISABLED | The performance counter is disabled and reset. |
1 | READ | The performance counter is incremented when a Read access is performed. |
2 | WRITE | The performance counter is incremented when a Write access is performed |
3 | CYCLE | Number of clock cycles |