39.5.7 GFX2D Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

Name: GFX2D_IM
Offset: 0x18
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
    IERRBERRRERREXENDRBEMPTY 
Access RRRRR 
Reset 00000 

Bit 4 – IERR Illegal Instruction Interrupt Mask Bit

Bit 3 – BERR Write Error Interrupt Mask Bit

Bit 2 – RERR Read Error Interrupt Mask Bit

Bit 1 – EXEND Execution Ended Empty Interrupt Mask Bit

Bit 0 – RBEMPTY Ring Buffer Empty Interrupt Mask Bit