39.5.8 GFX2D Interrupt Status Register
| Name: | GFX2D_IS |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IERR | BERR | RERR | EXEND | RBEMPTY | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – IERR Illegal Instruction Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | The interrupt source is masked or no Illegal Instruction interrupt is pending. |
| 1 | An Illegal Instruction interrupt is pending. |
Bit 3 – BERR Write Error Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | Either the interrupt source is masked or no Write Error interrupt is pending. |
| 1 | A Write Error interrupt is pending. |
Bit 2 – RERR Read Error Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | Either the interrupt source is masked or no read error interrupt is pending. |
| 1 | An interrupt is pending. |
Bit 1 – EXEND End of Execution Status Bit
| Value | Description |
|---|---|
| 0 | Either the interrupt source is masked or no End of Execution interrupt is pending. |
| 1 | An End of Execution interrupt is pending (i.e. EXEND is '1' when GFX2D_GS.BUSY is set to '0'). |
Bit 0 – RBEMPTY Ring Buffer Empty Interrupt Status Bit
| Value | Description |
|---|---|
| 0 | The Ring Buffer Empty interrupt has not occurred. |
| 1 | The Ring Buffer Empty interrupt has occurred since the last read of the status register. |