58.6.1.3 QSPI Timings

Timings are given in the following domains:

1.8V domain: VDDIO from 1.7V to 1.95V, maximum external capacitor = 15 pF, DRV= 1, SR = 0
3.3V domain: VDDIO from 3.00V to 3.6V, maximum external capacitor = 15 pF, DRV= 0, SR = 0

Table 58-20. QSPI Timings in Single Data Rate Mode⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
QSPI₀	QIOx data in to QSCK rising edge (input setup time)	3.3V domain	1.2	–	ns
QSPI₀	QIOx data in to QSCK rising edge (input setup time)	1.8V domain	1.1	–	ns
QSPI₁	QIOx data in to QSCK rising edge (input hold time)	3.3V domain	0.2	–	ns
QSPI₁	QIOx data in to QSCK rising edge (input hold time)	1.8V domain	0.2	–	ns
QSPI₂	QSCK rising edge to QIOx data out valid	3.3V domain	0	1.4	ns
QSPI₂	QSCK rising edge to QIOx data out valid	1.8V domain	0	1.9	ns
QSPI₃	QIOx data in to QSCK falling edge (input setup time)	3.3V domain	1.1	–	ns
QSPI₃	QIOx data in to QSCK falling edge (input setup time)	1.8V domain	1.1	–	ns
QSPI₄	QIOx data in to QSCK falling edge (input hold time)	3.3V domain	0.5	–	ns
QSPI₄	QIOx data in to QSCK falling edge (input hold time)	1.8V domain	0.4	–	ns
QSPI₅	QSCK falling edge to QIOx data out valid	3.3V domain	0	1.3	ns
QSPI₅	QSCK falling edge to QIOx data out valid	1.8V domain	0	1.6	ns

Note:

The data provided in this table are extracted from circuit simulation results.

In the following table:

t_HCLK is the HCLK period.
k is 0.25 if f_MCK = f_QSCK and k=0.5 when f_MCK ≥ f_QSCK

Table 58-21. QSPI Timings in Double Data Rate Mode⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
QSPI₁₀	QIOx data in to QSCK edge (rising or falling, input setup time)	3.3V domain	1.2	–	ns
QSPI₁₀		1.8V domain	1.4	–	ns
QSPI₁₁	QIOx data in to QSCK edge (rising or falling, input hold time)	3.3V domain	0.5	–	ns
QSPI₁₁		1.8V domain	0.4	–	ns
QSPI₁₂	QSCK edge (rising or falling) to QIOx data out valid	3.3V domain	k x T_HCLK -0.6	k x T_HCLK + 1.5	ns
QSPI₁₂	QSCK edge (rising or falling) to QIOx data out valid	1.8V domain	k x T_HCLK - 0.8	k x T_HCLK + 2.0	ns

Note:

The data provided in this table are extracted from circuit simulation results.

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