58.6.1.3 QSPI Timings

Timings are given in the following domains:
  • 1.8V domain: VDDIO from 1.7V to 1.95V, maximum external capacitor = 15 pF, DRV= 1, SR = 0
  • 3.3V domain: VDDIO from 3.00V to 3.6V, maximum external capacitor = 15 pF, DRV= 0, SR = 0

Table 58-20. QSPI Timings in Single Data Rate Mode(1)
Symbol Parameter Conditions Min Max Unit
QSPI0 QIOx data in to QSCK rising edge (input setup time) 3.3V domain 1.2 – ns
1.8V domain 1.1 – ns
QSPI1 QIOx data in to QSCK rising edge (input hold time) 3.3V domain 0.2 – ns
1.8V domain 0.2 – ns
QSPI2 QSCK rising edge to QIOx data out valid 3.3V domain 0 1.4 ns
1.8V domain 0 1.9 ns
QSPI3 QIOx data in to QSCK falling edge (input setup time) 3.3V domain 1.1 – ns
1.8V domain 1.1 – ns
QSPI4 QIOx data in to QSCK falling edge (input hold time) 3.3V domain 0.5 – ns
1.8V domain 0.4 – ns
QSPI5 QSCK falling edge to QIOx data out valid 3.3V domain 0 1.3 ns
1.8V domain 0 1.6 ns
Note:
  1. The data provided in this table are extracted from circuit simulation results.

In the following table:

  • tHCLK is the HCLK period.
  • k is 0.25 if fMCK = fQSCK and k=0.5 when fMCK ≥ fQSCK

Table 58-21. QSPI Timings in Double Data Rate Mode(1)
Symbol Parameter Conditions Min Max Unit
QSPI10 QIOx data in to QSCK edge (rising or falling, input setup time) 3.3V domain 1.2 – ns
1.8V domain 1.4 – ns
QSPI11 QIOx data in to QSCK edge (rising or falling, input hold time) 3.3V domain 0.5 – ns
1.8V domain 0.4 – ns
QSPI12 QSCK edge (rising or falling) to QIOx data out valid 3.3V domain k x THCLK -0.6 k x THCLK + 1.5 ns
1.8V domain k x THCLK - 0.8 k x THCLK + 2.0 ns
Note:
  1. The data provided in this table are extracted from circuit simulation results.