58.6.5.2 Write Timings

Table 58-30. SMC Write Signals - NWE-controlled (WRITE_MODE = 1)
Symbol	Parameter	Conditions	Min	Max	Unit
HOLD or NO HOLD SETTINGS (NWE_HOLD ≠ 0, NWE_HOLD = 0)
SMC₁₅	Data out valid before NWE high	3.3V domain	NWE_PULSE × t_CPMCK - 10.4	–	ns
SMC₁₅	Data out valid before NWE high	1.8V domain	NWE_PULSE × t_CPMCK - 9.4	–	ns
SMC₁₆	NWE pulse width	3.3V domain	NWE_PULSE × t_CPMCK - 2	–	ns
SMC₁₆	NWE pulse width	1.8V domain	NWE_PULSE × t_CPMCK - 0.3	–	ns
SMC₁₇	A0–A22 valid before NWE low	3.3V domain	NWE_SETUP × t_CPMCK - 10.5	–	ns
SMC₁₇	A0–A22 valid before NWE low	1.8V domain	NWE_SETUP × t_CPMCK - 9.2	–	ns
SMC₁₈	NCS low before NWE high	3.3V domain	(NWE_SETUP - NCS_RD_SETUP + NWE_PULSE) × t_CPMCK - 10.3	–	ns
SMC₁₈	NCS low before NWE high	1.8V domain	(NWE_SETUP - NCS_RD_SETUP + NWE_PULSE) × t_CPMCK - 8.8	–	ns
HOLD SETTINGS (NWE_HOLD ≠ 0)
SMC₁₉	NWE high to data OUT, NBS0/A0 NBS1, A1 - A23 change	3.3V domain	NWE_HOLD × t_CPMCK - 4.5	–	ns
SMC₁₉	NWE high to data OUT, NBS0/A0 NBS1, A1 - A23 change	1.8V domain	NWE_HOLD × t_CPMCK - 5.0	–	ns
SMC₂₀	NWE high to NCS inactive⁽¹⁾	3.3V domain	(NWE_HOLD - NCS_WR_HOLD) × t_CPMCK - 3.3	–	ns
SMC₂₀	NWE high to NCS inactive⁽¹⁾	1.8V domain	(NWE_HOLD - NCS_WR_HOLD) × t_CPMCK - 3.6	–	ns
NO HOLD SETTINGS (NWE_HOLD = 0)
SMC₂₁	NWE high to data OUT, NBS0/A0 NBS1, A1 - A23, NCS change⁽¹⁾	3.3V domain	- 4.7	–	ns
SMC₂₁	NWE high to data OUT, NBS0/A0 NBS1, A1 - A23, NCS change⁽¹⁾	1.8V domain	- 5.0	–	ns

Note:

Hold length = Total cycle duration - setup duration - pulse duration. "hold length" is for "NCS_WR_HOLD length" or "NWE_HOLD length".

Table 58-31. SMC Write Signals - NCS-Controlled (WRITE_MODE = 0)
Symbol	Parameter	Conditions	Min	Max	Unit
SMC₂₂	Data out valid before NCS high	3.3V domain	NCS_WR_PULSE × t_CPMCK - 9.3	–	ns
SMC₂₂	Data out valid before NCS high	1.8V domain	NCS_WR_PULSE × t_CPMCK - 7.8	–	ns
SMC₂₃	NCS pulse width	3.3V domain	NCS_WR_PULSE × t_CPMCK - 2.8	–	ns
SMC₂₃	NCS pulse width	1.8V domain	NCS_WR_PULSE × t_CPMCK - 1.5	–	ns
SMC₂₄	A0–A22 valid before NCS low	3.3V domain	NCS_WR_SETUP × t_CPMCK - 9.3	–	ns
SMC₂₄	A0–A22 valid before NCS low	1.8V domain	NCS_WR_SETUP × t_CPMCK - 7.9	–	ns
SMC₂₅	NWE low before NCS high	3.3V domain	(NCS_WR_SETUP - NWE_SETUP + NCS_PULSE) × t_CPMCK - 6.4	–	ns
SMC₂₅	NWE low before NCS high	1.8V domain	(NCS_WR_SETUP - NWE_SETUP + NCS_PULSE) × t_CPMCK - 4.8	–	ns
SMC₂₆	NCS high to data OUT, A0 - A25 change	3.3V domain	NCS_WR_HOLD × t_CPMCK - 8.6	–	ns
SMC₂₆	NCS high to data OUT, A0 - A25 change	1.8V domain	NCS_WR_HOLD × t_CPMCK - 9.1	–	ns
SMC₂₇	NCS high to NWE Inactive	3.3V domain	(NCS_WR_HOLD - NWE_HOLD) × t_CPMCK - 8.6	–	ns
SMC₂₇	NCS high to NWE Inactive	1.8V domain	(NCS_WR_HOLD - NWE_HOLD) × t_CPMCK - 8.5	–	ns

Figure 58-19. SMC Timings - NCS-controlled Read and Write

Figure 58-20. SMC Timings - NRD-controlled Read and NEW-controlled Write