44.6.2.8 Conversion Timing and Sampling Rate

The following figure shows the ADC timing for one single conversion. A conversion starts after the software or event start are synchronized with the GCLK_ADC clock. The input channel is sampled in the first half CLK_ADC period.

Figure 44-3. ADC Timing for One Conversion in 12-bit Resolution
Note: Refer to the tables in the ADC Electrical Specifications chapter to get the different conversion times for 8-bit, 10-bit, and 12-bit resolution.

The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion with sampling time increased to six CLK_ADC cycles.

Figure 44-4. ADC Timing for One Conversion with Increased Sampling Time, 12-bit

The ADC provides also offset compensation, see the following figure. The offset compensation is enabled by the Offset Compensation bit in the Sampling Control register (SAMPCTRL.OFFCOMP).

Note: ADC sampling time is fixed to 4 ADC Clock cycles when offset compensation (OFFCOMP=1) is used.
Figure 44-5. ADC Timing for One Conversion with Offset Compensation, 12-bit

The following figure shows the ADC timing for free-running mode conversion.

Figure 44-6. ADC Timing for Free Running in 12-bit Resolution

In free running mode, the sampling rate RS is calculated by

RS = fCLK_ADC / ( nSAMPLING + nOFFCOMP + nDATA)

Here, nSAMPLING is the sampling duration in CLK_ADC cycles, nOFFCOMP is the offset compensation duration in clock cycles, and nDATA is the bit resolution. fCLK_ADC is the ADC clock frequency from the internal prescaler: fCLK_ADC = fGCLK_ADC / 2^(1 + CTRLB.PRESCALER)

The propagation delay of an ADC measurement is given by:

PropagationDelay = 1 + Resolution f ADC
Example. In order to obtain 1MSPS in 12-bit resolution with a sampling time length of four CLK_ADC cycles, fCLK_ADC must be 1MSPS * (4 + 12) = 16MHz. As the minimal division factor of the prescaler is 2, GCLK_ADC must be 32MHz.