21.6.8 VREGPLL Voltage Regulator System Control
| Name: | VREGPLL |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| STARTUP[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 11:8 – STARTUP[3:0] Startup Time
These bits define the VREGPLL wake-up counts, using the 32.768 kHz Ultra Low Power Oscillator (OSCULP32K) output.
The startup time is calculated as: Startup_Time = (STARTUP + 1) * osculp32k_period.
The STARTUP register value must comply with the requirement: STARTUP ≥ (CEXT_TYP + CEXT_ERR)/ 1μF, where CEXT_TYP represents the typical external capacitor connected to VDDPLL, and CEXT_ERR represents the accuracy error of the external capacitor.
Bit 6 – RUNSTDBY Run In Standby
| Value | Description |
|---|---|
| 0 | In Standby sleep mode, the VREGPLL voltage regulator is enabled only during a sleep walking task execution and if VREGPLL.ENABLE = 1. |
| 1 | In Standby sleep mode, the VREGPLL voltage regulator is always enabled if VREGPLL.ENABLE = 1. |
Bit 1 – ENABLE Enable
| Value | Description |
|---|---|
| 0 | VREGPLL voltage regulator is disabled. |
| 1 | VREGPLL voltage regulator is enabled. |