10.1.8.11 LVDS PHY Characteristics

The SAM9X7 Series complies with the LVDS standard TIA/EIA-644 for protocol and electrical specifications.

Table 10-59. LVDS PHY Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	3.60	V
I_DDIN33	Current consumption (VDDIN33)⁽²⁾⁽³⁾	Pre-emphasis disabled	–	30.0	mA
I_DDIN33	Current consumption (VDDIN33)⁽²⁾⁽³⁾	Pre-emphasis enabled	–	50.0	mA
t_START	Start-up time⁽²⁾	–	–	50	μs
V_OD	Output differential voltage⁽²⁾	–	+/-250	+/-450	mV
V_CM	Output common mode voltage	–	1.06	1.44	V
V_OHS	Single-ended output level high⁽²⁾	–	1.21	1.64	V
V_OLS	Single-ended output level low	–	0.91	1.24	V
f_LVDSCK	LVDS_CLK1x output frequency⁽²⁾	–	57	79	MHz
BR_LANE	Bit rate per lane⁽⁴⁾	–	175	550	Mbps

Note:

This LVDS PHY must be powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
Simulation data
Four-lane data stream, 0.4 Mbps/lane, 100 Ohms load
Maximum LVDS PHY operating data rate. From a system point of view, the display resolution is limited to 1280x720.