8.4.7.19 QSPI Timeout Register

This register can only be written if the WPEN bit is cleared in the QSPI Write Protection Mode Register.

Name:	QSPI_TOUT
Offset:	0x64
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	TCNTM[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TCNTM[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – TCNTM[15:0] Time-out Counter Maximum Value

Indicates the time in GCLK clock periods when the connected client does not answer and before the TOUT flag is set.

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