The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
QSPI_IMR
Offset:
0x1C
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
TOUT
RFRSHD
Access
R
R
Reset
0
0
Bit
15
14
13
12
11
10
9
8
CSRA
CSFA
QITR
QITF
LWRA
INSTRE
CSF
CSR
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OVRES
TXEMPTY
TDRE
RDRF
Access
R
R
R
R
Reset
0
0
0
0
Bit 17 – TOUT QSPI Time-out Interrupt Mask
Bit 16 – RFRSHD Refresh Done Interrupt Mask
Bit 15 – CSRA Chip Select Rise Autoclear Interrupt Mask
Bit 14 – CSFA Chip Select Fall Autoclear Interrupt Mask
Bit 13 – QITR QSPI Interrupt Rise Interrupt Mask
Bit 12 – QITF QSPI Interrupt Fall Interrupt Mask
Bit 11 – LWRA Last Write Access Interrupt Mask
Bit 10 – INSTRE Instruction End Interrupt Mask
Bit 9 – CSF Chip Select Fall Interrupt
Mask
Bit 8 – CSR Chip Select Rise Interrupt Mask
Bit 3 – OVRES Overrun Error Interrupt Mask
Bit 2 – TXEMPTY Transmission Registers Empty Mask
Bit 1 – TDRE Transmit Data Register Empty Interrupt Mask
Bit 0 – RDRF Receive Data Register Full Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
