8.4.7.1 QSPI Control Register

This register can only be written if the WPCREN bit is cleared in the QSPI Write Protection Mode Register.

Name: QSPI_CR
Offset: 0x00
Reset: –
Property: Write-only

Bit 3130292827262524 
        LASTXFER 
Access W 
Reset – 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
      RTOUTSTTFRUPDCFG 
Access WWW 
Reset ––– 
Bit 76543210 
 SWRST SRFRSH   QSPIDISQSPIEN 
Access WWWW 
Reset –––– 

Bit 24 – LASTXFER Last Transfer

ValueDescription
0 No effect.
1 The chip select is deasserted after the end of character transmission.

Bit 10 – RTOUT Reset Time-out

ValueDescription
0 No effect.
1 Request a TOUT flag reset.

Bit 9 – STTFR Start Transfer

ValueDescription
0 No effect.
1 Starts the transfer when TFRTYP=0 and SMRM=1 or when DATAEN=0.

Bit 8 – UPDCFG Update Configuration

ValueDescription
0 No effect.
1 Requests an update of the QSPI Controller core configuration.

Bit 7 – SWRST QSPI Software Reset

DMA channels state are not affected by a software reset.

ValueDescription
0 No effect.
1 Resets the QSPI. A software reset of the QSPI interface is performed.

Bit 5 – SRFRSH Start Refresh

ValueDescription
0 No effect.
1 Starts a refresh sequence. QSPI_ISR.RFRSHD indicates when the refresh sequence is over.

Bit 1 – QSPIDIS QSPI Disable

As soon as QSPIDIS is set, the QSPI finishes its transfer.

All pins are set in Input mode and no data is received or transmitted.

If a transfer is in progress, the transfer is finished before the QSPI is disabled.

If QSPIEN and QSPIDIS are set to 1 when QSPI_CR is written, the QSPI is disabled.

ValueDescription
0 No effect.
1 Disables the QSPI.

Bit 0 – QSPIEN QSPI Enable

ValueDescription
0 No effect.
1 Enables the QSPI.