3.3.20.7 SMC Off-Chip Memory Scrambling Key2 Register

This register is a ‘Write-once’ register: the first write access after a system reset prevents any further modification of the register value.

This register is erased if a tamper is detected on fast wake-up pins and bit SMC_OCMS.TAMPCLR = 1.

Name: SMC_KEY2
Offset: 0x88
Reset: 0x00000000
Property: Write-only

Bit 3130292827262524 
 KEY2[31:24] 
Access WWWWWWWW 
Reset 00000000 
Bit 2322212019181716 
 KEY2[23:16] 
Access WWWWWWWW 
Reset 00000000 
Bit 15141312111098 
 KEY2[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 KEY2[7:0] 
Access WWWWWWWW 
Reset 00000000 

Bits 31:0 – KEY2[31:0] Off-Chip Memory Scrambling (OCMS) Key Part 2

When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling.