16.5.7.5.3 SPI Clock Frequency, Phase and Polarity (MRL A, MRL B)
The peripheral clock of each QSPI controller is gated from the Main System Bus clock (MCK). The ROM code configures MCK and the QSPI Serial Clock (QSCK). See the table "Clock Frequencies during External Memory Boot Sequence".
The QSPI controller is configured to use Clock mode 0: Both CPHA and CPOL are cleared in
QSPI_SCR.
- CPOL = 0: The inactive state value of QSCK is logic level zero.
- CPHA = 0: Data is captured on the leading edge of QSCK and changed on the following edge of QSCK.