16.5.7.5.4 QSPI Memory Detection (MRL A, MRL B)

The ROM code probes the QSPI memory using JEDEC Read ID commands. However the opcode and the SPI protocol to be used to read the JEDEC ID of the QSPI memory depend on its Manufacturer and its current internal state.

Cypress

Cypress memories do not support the SPI 4-4-4 protocol. The command opcode is always sent on the single MOSI/IO1 data line. Hence when writing the 9Fh opcode on MOSI during the first 8 cycles, Cypress memories should always reply on MISO with their JEDEC ID during the following cycles.

Micron

Micron memories provide three modes of operation:
  • Extended SPI: standard SPI protocol upgraded with dual (SPI 1-1-2, SPI 1-2-2) and quad (SPI 1-1-4, SPI 1-4-4) operations
  • Dual I/O SPI: all commands use the SPI 2-2-2 protocol
  • Quad I/O SPI: all commands use the SPI 4-4-4 protocol
The ROM code supports the Extended and Quad I/O SPI modes but not Dual I/O SPI.

In Extended SPI mode, Micron memories replies to the regular Read JEDEC ID opcode using the protocol SPI 1-1-1: the 9Fh opcode is sent on MOSI using eight clock cycles then the JEDEC ID is read from MISO only.

In Quad I/O SPI mode, Micron memories no longer reply to the regular Read JEDEC ID (9Fh) but answer the new Read JEDEC ID Multiple I/O command instead: The AFh op code is sent on the 4 I/O lines using 2 clock cycles, then only the 3 first bytes (1 byte for the Manufacturer ID followed by 2 bytes for the Device ID) of the JEDEC ID are returned by the memory on the 4 I/O lines.

The AFh opcode is not supported in Extended SPI mode.

Macronix

Macronix memories provide two modes of operation:
  • SPI: standard SPI protocol upgraded with dual (SPI 1-1-2, SPI 1-2-2) and quad (SPI 1-1-4, SPI 1-4-4) operations
  • QPI: all commands use the SPI 4-4-4 protocol

The ROM code supports only the Macronix SPI mode.

In SPI mode, Macronix memories reply to the regular Read JEDEC ID opcode using the protocol SPI 1-1-1: The 9Fh opcode is sent on MOSI using 8 clock cycles then the JEDEC ID is read from MISO only.

Hence the ROM code uses the following sequence to read the JEDEC ID:

Step SPI Protocol Opcode Support by Manufacturer Modes
1 1-1-1 9Fh Cypress, Micron Extended SPI, Macronix SPI
2 1-4-4 AFh See Note below
3 4-4-4 AFh Micron Quad I/O SPI
Note: Step 2 is a wrong combination but should not change the internal state of any QSPI memory. Indeed, assuming pull-up resistors are used on the four I/O lines, sending the AFh op code with SPI 1-x-y protocols (the opcode is sent only to MOSI during eight clock cycles) to a memory in Quad I/O SPI or QPI mode should be harmless (FEh opcode decoded by the memory when in Quad I/O SPI or QPI mode: unknown opcode). See the figure below.
Figure 16-10. QSPI Transfer Format (CPHA = 0, 8 bits per opcode)