16.5.7.5.6 Configuration of Fast Read Quad I/O (EBh) Operations (MRL A, MRL B)

The ROM code performs all read operations using the Fast Read Quad I/O (EBh) opcode followed by a 3-byte address.

Since we cannot afford to add an exhaustive table of Read JEDEC IDs and to provide support of future products of memory manufacturers, the ROM code only relies on the very first byte of the JEDEC ID, i.e., the Manufacturer ID, to configure read operations. The ROM code matches the Manufacturer ID as shown in the following table.

Table 16-2. Fast Read Quad I/O (EBh) Configuration by Manufacturer ID
Manufacturer ID Manufacturer SPI Protocol # of Mode Cycles # of Dummy Cycles Mode Cycle Value
(no XIP) (XIP)
01h Cypress SPI 1-4-4 2 (1) 4 (1) 00h A0h
20h Micron SPI 4-4-4 1 (2) 9 (2) 1h 0h
C2h Macronix SPI 1-4-4 2 (3) 4 (3) 00h F0h
Note:
  1. The ROM code expects the Latency Control non-volatile bits of the Cypress Status Register 3 (SR3) / Control Register 1 (CR1) to be zero (LC = 0). The ROM code does not update this value.
  2. The ROM code sets the number of mode/dummy cycles for Micron memories updating bits [7:4] of their Volatile Configuration Register (VCR) with the 81h opcode. During this update of the VCR:
    • ROM code v1.1 always clears bit3 to enable XIP.
    • ROM code v1.2 clears bit3 to enable XIP if and only if XIP bit is set in the Boot Config word, otherwise it sets bit3 to disable XIP.
  3. The ROM code configures the number of mode/dummy cycles for Macronix memories by clearing the volatile DC0 and DC1 bits (bits [7:6]) in the Configuration Register (CR) / Status Register 2 (SR2). It also clears the 4-byte volatile bit (bit5), resulting in the memory going back to its 3-byte address mode. This register updated (read, modify, write) using a Write Status command (01h).