SAMA5D2 Series

66.4.2 Main System Bus Clock Characteristics

The main system bus clock is the maximum clock at which the system is able to run. It is given by the smallest value of the internal bus clock and EBI clock.

Table 66-16. Main System Bus Clock Waveform Parameters
Symbol	Parameter	Conditions	Min	Max	Unit
1/(t_CPMCK)	Main System Bus Clock Frequency	VDDCORE[1.1V, 1.32V]	125⁽¹⁾	133	MHz
1/(t_CPMCK)	Main System Bus Clock Frequency	VDDCORE[1.2V, 1.32V], in DDR2 or LPDDR1 mode, VDDIODDR[1.8V, 1.9V] in LPDDR2 or LPDDR3 mode, VDDIODDR[1.2V, 1.30V] in DDR3 mode, VDDIODDR[1.5V, 1.575V] in DDR3L mode, VDDIODDR[1.35V, 1.45V] Security disabled	125⁽¹⁾	166⁽²⁾	MHz

Note:

Limitation for DDR2 usage only. There are no limitations to DDR3, DDR3L, LPDDR1, LPDDR2 and LPDDR3.
The JEDEC standard specifies a maximum clock frequency of 125 MHz for DDR3 and DDR3L in DLL Off mode. However, check with memory suppliers for higher frequencies.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.