37.4.6 I3CxSTAT1
Note:
- In case of a race condition, user writes always take precedence over hardware events.
| Name: | I3CxSTAT1 |
| Address: | 0x088, 0x0BB |
Status 1
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXFNE | |||||||||
| Access | R/HS/HC | ||||||||
| Reset | 0 |
Bit 0 – TXFNE Transmit FIFO Not Empty
| Value | Description |
|---|---|
| 1 | The Transmit FIFO is not empty |
| 0 | The Transmit FIFO is empty |