37.2.3.4.3 Bus Idle Condition

The Bus Idle condition is defined as a period during which the Bus Available condition is sustained continuously for a duration of at least TIDLE duration as specified in Table 37-4 below. This time is specified by the user using the I3CxBIDL Bus Idle Condition Threshold Register. An internal counter incremented by the I3CxCLK clock is compared against the value in the I3CxBIDL register to determine when a Bus Idle condition occurs. This counter stops counting at the I3CxBIDL value and resets at every Stop condition.

For example, for I3CxCLK = FOSC = 64 MHz, a TIDLE of 200 µs duration takes 12,800 counts. Hence, the user must set I3CxBIDL = 12800 during setup for I3C to operate as expected. Table 37-5 below contains I3CxBIDL values for commonly used I3CxCLK clock speeds for reference.

The Bus Idle condition is key to ensuring bus stability when new devices are added to the bus during Hot-Join events.

CAUTION: The user must set appropriate values in the I3CxBAVL and I3CxBIDL registers during setup to match the I3C bus condition timings as specified in Table 37-4 for the module to operate as expected. Failing to do so may result in unexpected behavior.
Table 37-4. Bus Condition Timings as per MIPI I3C Specification Basic v1.0
Bus Condition Symbol Timing
Bus Free Condition TCAS for pure bus 38.4 ns
TBUF for mixed bus

1.3 µs for Fast mode (400 kHz)

500 ns for Fast mode Plus (1 MHz)
Bus Available Condition TAVAL 1 µs
Bus Idle Condition TIDLE 200 µs
Table 37-5. I3CxBAVL and I3CxBIDL Values for Commonly Used I3CxCLK Clock Speeds
I3CxCLK Clock Speed I3CxBAVL Value for TAVAL = 1 µs I3CxBIDL Value for TIDLE = 200 µs
8 MHz 8 1600
16 MHz 16 3200
32 MHz 32 6400
48 MHz 48 9600
64 MHz 64 12800
Figure 37-6. I3C® Bus Condition Timings