37.4.17 I3CxBAVL
Note:
- The value of this register is determined as the number of I3CxCLK clocks corresponding to the Bus Available Condition. An internal counter incremented by the I3CxCLK clock is compared against this value to determine when a Bus Available Condition occurs.
- To guarantee expected behavior, this register should only be written when
the module is disabled (EN =
0).
| Name: | I3CxBAVL |
| Address: | 0x094, 0x0C7 |
Bus Available Condition Threshold
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BAVL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |