The value of this register is determined as the number of I3CxCLK clocks corresponding to the Bus Idle
Condition. An internal counter incremented by the I3CxCLK clock
is compared against this value to determine when a Bus Idle Condition
occurs.
To guarantee expected behavior, this register should only be written when
the module is disabled (EN = 0).
Name:
I3CxBIDL
Address:
0x092, 0x0C5
Bus Idle Condition
Threshold
Bit
15
14
13
12
11
10
9
8
BIDL[15:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BIDL[15:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – BIDL[15:0]
Bus Idle Condition Threshold
The value of this register is determined as the number of I3CxCLKI3CxCLK clocks corresponding to the Bus Idle
Condition. An internal counter incremented by the I3CxCLK clock
is compared against this value to determine when a Bus Idle Condition
occurs.
To guarantee expected behavior, this register should only be written when
the module is disabled (EN Target Enable = 0).
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