11.13.35 PIR12

Peripheral Interrupt Request Register 12

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software will ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
U4IF is a read-only bit. To clear the interrupt condition, all bits in the U4UIR register must be cleared.
U4EIF is a read-only bit. To clear the interrupt condition, all bits in the U4ERR register must be cleared.
U4TXIF and U4RXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR12
Address:	0x4BA


Bit	7	6	5	4	3	2	1	0
	DMA5AIF	DMA5ORIF	DMA5DCNTIF	DMA5SCNTIF	U4IF	U4EIF	U4TXIF	U4RXIF
Access	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – DMA5AIF DMA5 Abort Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – DMA5ORIF DMA5 Overrun Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – DMA5DCNTIF DMA5 Destination Count Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – DMA5SCNTIF DMA5 Source Count Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – U4IF UART 4 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – U4EIF UART4 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – U4TXIF UART4 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – U4RXIF UART4 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software will ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U4IF is a read-only bit. To clear the interrupt condition, all bits in the U4UIR register must be cleared. U4EIF is a read-only bit. To clear the interrupt condition, all bits in the U4ERR register must be cleared. U4TXIF and U4RXIF are read-only bits and cannot be set/cleared by software.