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11.13.41 IPR2
Peripheral Interrupt
Priority Register 2| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | DMA1AIP | DMA1ORIP | DMA1DCNTIP | DMA1SCNTIP | | | | ADTIP | |
| Access | R/W | R/W | R/W | R/W | | | | R/W | |
| Reset | 1 | 1 | 1 | 1 | | | | 1 | |
Bit 7 – DMA1AIP DMA1 Abort
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 6 – DMA1ORIP DMA1 Overrun
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 5 – DMA1DCNTIP DMA1 Destination
Count Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 4 – DMA1SCNTIP DMA1 Source Count
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 0 – ADTIP ADC Threshold
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
