11.13.27 PIR4
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software will ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
- PWM1IF is a read-only bit. To clear the interrupt condition, all bits in the PWM1GIR register must be cleared.
- U1IF is a read-only bit. To clear the interrupt condition, all bits in the U1UIR register must be cleared.
- U1EIF is a read-only bit. To clear the interrupt condition, all bits in the U1ERR register must be cleared.
- U1TXIF and U1RXIF are read-only bits and cannot be set/cleared by software.
| Name: | PIR4 |
| Address: | 0x4B2 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWM1IF | PWM1PIF | U1IF | U1EIF | U1TXIF | U1RXIF | ||||
| Access | R | R/W/HS | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – PWM1IF PWM1 Parameter Interrupt Flag(2)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 6 – PWM1PIF PWM1 Period Interrupt Flag
| Value | Description |
|---|---|
| 1 | Interrupt has occurred (must be cleared by software) |
| 0 | Interrupt event has not occurred |
Bit 3 – U1IF UART1 Interrupt Flag(3)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 2 – U1EIF UART1 Framing Error Interrupt Flag(4)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 1 – U1TXIF UART1 Transmit Interrupt Flag(5)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |
Bit 0 – U1RXIF UART 1 Receive Interrupt Flag(5)
| Value | Description |
|---|---|
| 1 | Interrupt has occurred |
| 0 | Interrupt event has not occurred |