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11.13.48 IPR9
Peripheral Interrupt
Priority Register 9| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | CLC4IP | | U3IP | U3EIP | U3TXIP | U3RXIP | |
| Access | | | R/W | | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | | 1 | 1 | 1 | 1 | |
Bit 5 – CLC4IP CLC4 Priority
Flag
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 3 – U3IP UART3 Interrupt
Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 2 – U3EIP UART3 Framing Error
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 1 – U3TXIP UART3 Transmit
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 0 – U3RXIP UART3 Receive
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
