14.12.7 SCANCON0

Scanner Access Control Register 0
Note:
  1. Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content.
  2. This bit is cleared when LADR > HADR (and a data cycle is not occurring).
  3. If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.
  4. BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.
  5. See Table 14-1 for more detailed information.
  6. An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls over. An invalid address can also occur if the value in the Scan Low address registers points to a location that is not mapped in the memory map of the device.
  7. CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to Program Memory Scan Configuration.
Name: SCANCON0
Offset: 0xF4F

Bit 76543210 
 SCANENSCANGOBUSYINVALIDINTM MODE[1:0] 
Access R/WR/W/HCRRR/WR/WR/W 
Reset 0001000 

Bit 7 – SCANEN  Scanner Enable bit(1)

ValueDescription
1 Scanner is enabled
0 Scanner is disabled, internal states are reset

Bit 6 – SCANGO  Scanner GO bit(2, 3)

ValueDescription
1 When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed to the client peripheral.
0 Scanner operations will not occur

Bit 5 – BUSY  Scanner Busy Indicator bit(4)

ValueDescription
1 Scanner cycle is in process
0 Scanner cycle is complete (or never started)

Bit 4 – INVALID Scanner Abort Signal bit

ValueDescription
1

SCANLADRL/H/U has incremented to an invalid address(6) or the scanner was not set up correctly(7)
0

SCANLADRL/H/U points to a valid address

Bit 3 – INTM NVM Scanner Interrupt Management Mode Select bit

ValueNameDescription
X MODE = 10 This bit is ignored
1 MODE = 01 CPU is stalled until all data is transferred. SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from interrupt
0 MODE = 01 CPU is stalled until all data is transferred. SCANGO is not affected by interrupts, the interrupt response will be affected
1 MODE = 00 OR 11

SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning from interrupt
0 MODE = 00 OR 11

Interrupts do not prevent NVM access

Bits 1:0 – MODE[1:0]  Memory Access Mode bits(5)

ValueDescription
11 Triggered mode
10 Peek mode
01 Burst mode
00 Concurrent mode
Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content. This bit is cleared when LADR > HADR (and a data cycle is not occurring). If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response. BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal. See Table   1 for more detailed information. An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls over. An invalid address can also occur if the value in the Scan Low address registers points to a location that is not mapped in the memory map of the device. CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to Program Memory Scan Configuration.