15.13.2 PIR0

Peripheral Interrupt Request (Flag) Register 0

Note:

Interrupts are not disabled by the PEIE bit.
IOCIF is a read-only bit; to clear the interrupt condition, all bits in the IOCF register must be cleared.
The external interrupt GPIO pin is selected by the INTPPS register.

Name:	PIR0
Offset:	0xECA


Bit	7	6	5	4	3	2	1	0
			TMR0IF	IOCIF		INT2IF	INT1IF	INT0IF
Access			R/W	R		R/W	R/W	R/W
Reset			0	0		0	0	0

Bit 5 – TMR0IF Timer0 Interrupt Flag bit⁽¹⁾

Value	Description
1	TMR0 register has overflowed (must be cleared by software)
0	TMR0 register has not overflowed

Bit 4 – IOCIF Interrupt-on-Change Flag bit^(1,2)

Value	Description
1	IOC event has occurred (must be cleared by software)
0	IOC event has not occurred

Bits 0, 1, 2 – INTxIF External Interrupt ‘x’ Flag bit^(1,3)

Value	Description
1	External Interrupt ‘x’ has occurred
0	External Interrupt ‘x’ has not occurred

Interrupts are not disabled by the PEIEPeripheral Interrupt Enable bit bit.IOCIF is a read-only bit; to clear the interrupt condition, all bits in the IOCF register must be cleared.The external interrupt GPIO pin is selected by the INTPPS register.

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