15.13.2 PIR0

Peripheral Interrupt Request (Flag) Register 0
Note:
  1. Interrupts are not disabled by the PEIE bit.
  2. IOCIF is a read-only bit; to clear the interrupt condition, all bits in the IOCF register must be cleared.
  3. The external interrupt GPIO pin is selected by the INTPPS register.
Name: PIR0
Offset: 0xECA

Bit 76543210 
   TMR0IFIOCIF INT2IFINT1IFINT0IF 
Access R/WRR/WR/WR/W 
Reset 00000 

Bit 5 – TMR0IF  Timer0 Interrupt Flag bit(1)

ValueDescription
1 TMR0 register has overflowed (must be cleared by software)
0 TMR0 register has not overflowed

Bit 4 – IOCIF  Interrupt-on-Change Flag bit(1,2)

ValueDescription
1 IOC event has occurred (must be cleared by software)
0 IOC event has not occurred

Bits 0, 1, 2 – INTxIF  External Interrupt ‘x’ Flag bit(1,3)

ValueDescription
1 External Interrupt ‘x’ has occurred
0 External Interrupt ‘x’ has not occurred
Interrupts are not disabled by the PEIEPeripheral Interrupt Enable bit bit.IOCIF is a read-only bit; to clear the interrupt condition, all bits in the IOCF register must be cleared.The external interrupt GPIO pin is selected by the INTPPS register.