1.1.1 Transceiver Low-Power

The Transceiver Quad and External PLLs have several registers that power down different parts of the circuitry. This allows enabling only the circuits that are used in the design to reduce the transceiver power.

The following table lists the registers that are required to disable parts of the Transceiver quad circuitry and external PLL circuitry.

Table 1-1. Transceiver Quad Circuitry
RegisterField NameValue for Low-PowerDescription
DES_RSTPDRXPD1Power down the Rx circuitry
PDDFE1Power down the DFE circuitry
PDEM1Power down the Eye Monitor circuitry
RCVEN1Disable RX receiver
DES_PKDETRXPKDETEN0Disable the RX peak detector
DES_IN_TERMRXTEN0Disable RX termination resistor
DES_RXPLL_DIVCDR_GAIN0Set CDR Gain to 0
DES_DFE_CAL_CTRL_0EN_OFFSET_CAL0Disable offset calibration
SER_RSTPDTXPD1Power down the TX circuitry
SER_TERM_CTRLTXTEN0Disable the TX termination resistor
SERDES_RTTRTT_CURRENT_PROG0Disable RTT trim circuitry
TXPLL_CTRLTXPLL_AUXDIVPD1Disable the AUX clock output
TXPLL_VBGREF_SEL0Disable the TX voltage regulator
TXPLL_PD1Disable TX PLL
TXPLL_CLKBUFTXPLL_DUALCLK1_MODE0Disable the refclkp input buffer
TXPLL_DUALCLK0_MODE0Disable the refclkn input buffer
TXPLL_DUALCLK1_ENTERM0Disable the refclkp input buffer single ended termination
TXPLL_DUALCLK0_ENTERM0Disable the refclkn input buffer single ended termination
EXTPLL_CLKBUF_EN_RDIFF0Disable 100Ω differential termination between refclkp and refclkn
Table 1-2. External PLL Circuitry
RegisterField NameValue for Low-PowerDescription
EXTPLL_CTRLEXTPLL_PD1Power down the External PLL
EXTPLL_VBGREF_SEL0Disable the TX voltage regulator
EXTPLL_CLKBUFEXTPLL_DUALCLK1_MODE0Disable the refclkp input buffer
EXTPLL_DUALCLK0_MODE0Disable the refclkn input buffer
EXTPLL_DUALCLK1_ENTERM0Disable the refclkp input buffer single ended termination
EXTPLL_DUALCLK0_ENTERM0Disable the refclkn input buffer single ended termination
EXTPLL_CLKBUF_EN_APAD0Disable analog connection to refclkn pad
EXTPLL_CLKBUF_EN_RDIFF0Disable 100Ω differential termination between refclkp and refclkn
Important: For more information about register configuration, see AN4592: PolarFire FPGA Dynamic Reconfiguration Interface Application Note and PolarFire Device Register Map