1.4.1.1 PLL Power Down

The Active low-power down input (PLL_POWERDOWN_N) can be exposed using CCC configurator. The PLL_POWERDOWN_N is an asynchronous signal, which can be used to reset the PLL from the FPGA fabric, which forces the PLL to its lowest power state and the clock outputs are driven Low.

In the design, this port is exposed and connected to DIP1 switch.

  • DIP1-0: Power Down Mode
  • DIP1-1: Normal Mode

The following figure shows the PF_CCC configurator settings for the demo design.

Figure 1-6. PLL Power Down—CCC Configurator Settings
Important: For Normal demo design, select Maximize VCO for Lowest Jitter in the CCC configurator.