1.4.1.2 Clock Gating

Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree. Pruning the clock disables portions of the circuitry, hence the flip-flops in them do not have to switch states. Gate enable/disable pins can be exposed by using the CCC configurator.

The design has a clock gating enable/disable switch, which is connected to DIP2 for OUTPUT0, 1, and 2.

  • DIP2-1: Clock Gating Enabled (Clock is available)
  • DIP2-0: Clock Gating Disabled (Clock is not available)

The following figure shows the PF_CCC configurator settings for the demo design.

Figure 1-7. Clock Gating—CCC Configurator Settings