2.5 PCIe/XAUI Fabric SPLL Configuration

The SPLL configuration fields are relevant only for PCIe and XAUI protocols (Figure 2-5). For the PCIe protocol, enter a valid value between 20 and 200 MHz for the CLK_BASE frequency.

For the XAUI protocol, the CLK_BASE frequency is read-only and fixed at 156.25 MHz.