2.4 Lane Configuration

Use Lane Configuration to configure up to four lanes for your SerDes. The SerDes can be configured to run in dual-protocol mode. See Table 2-1 for lane configuration for dual mode operation.

Figure 2-5. High Speed Serial Interface Configurator
  • Speed—Available selections depend on your selected Protocol. See Table 2-1 for the valid speeds.
  • Reference Clock Source—Two clock sources are available: REFCLK0 and REFCLK1. Each can be differential or single-ended. You can select one of the following options for Protocol 1 and Protocol 2:
    • REFCLK0 (Differential),
    • REFCLK1 (Differential),
    • REFCLK0 (Single-Ended),
    • REFCLK1 (Single-Ended)
    • Fabric (Available only for EPCS Protocol)
    Note: Lane 0 and 1 share the same reference clock and Lane 2 and 3 share the same reference clock. The selected reference clock is always available as REFCLK0_OUT or REFCLK1_OUT and can be used as clock source for logic inside fabric.
  • PHY RefClk Frequency (MHz)—This is a fixed value for all protocols except EPCS Custom Speed, in which case you can enter values between 100 and 160 MHz.
  • Data Rate (Mbps)—Read-only fixed value for all protocols except EPCS custom speed, in which case you can select the data rate from the list. Data rates are computed based on the PHY RefClk frequency.
  • Data Width—Read-only fixed value for all protocols except EPCS custom speed. For EPCS, the data width varies with data rate (Mbps) as follows:
    • 20 bits (for 5000 Mbps and 2500 Mbps)
    • 16 bits (for 4000 Mbps or 2000 Mbps)
    • 10 bits (2500 Mbps or 1250 Mbps)
    • 8 bits (for 2000 Mbps or 1000 Mbps)
    • 5 bits (for 1250 Mbps)
    • 4 bits (for 1000 Mbps)
    The displayed value is computed and updated based on your selected PHY RefClk frequency and data rate.
  • FPGA Interface Frequency (MHz)—Read-only fixed value for all protocols except EPCS custom speed. The displayed value is computed and updated based on the PHY RefClk frequency and data rate you select.
  • VCO Rate (MHz)—Read-only fixed value for all protocols except EPCS custom speed. The displayed value is computed and updated based on the PHY RefClk frequency and data rate you select.