2.12 Simulation Level

There are three levels of ModelSim simulation supported for the High Speed Serial Interface block depending on the selected protocol. See the SmartFusion2 FPGA High Speed Serial Interface Simulation User Guide for more information.

• BFM_CFG—This level provides a bus functional model of only the APB configuration bus of the High Speed Serial Interface block. You can write and read the different configuration and status bits from the High Speed Serial Interface block through its APB slave interface. The status bits value does not change based on the APB state; they are kept at their reset values. This simulation level is available for all protocols.
• BFM_PCIe—This simulation level provides the BFM_CFG level plus the ability to communicate with the High Speed Serial Interface block through the master and slave AXI or AHB bus interfaces. Although, no serial communication actually goes through the High Speed Serial Interface block, this scenario enables you to validate the fabric interface connections. This simulation level is only available for the PCIe protocol.
• RTL—This simulation level enables you to fully simulate the High Speed Serial Interface block from the fabric interface to the serial data interface. This results in a longer simulation run time. This simulation level is available for all protocols.