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SmartFusion®2 and IGLOO®2 High-Speed Serial Interface Configuration User Guide Libero® SoC v2021.2
SmartFusion®2 and IGLOO®2 High-Speed Serial Interface Configuration User Guide Libero® SoC v2021.2
  1. Home
  2. 2 Functionality
  3. 2.10 High Speed Serial Interface Control Registers

Libero® SoC v2021.2

  • Introduction
  • 1 Overview
  • 2 Functionality
    • 2.1 Identification
    • 2.2 Protocol Configuration
    • 2.3 Configure PCIe
    • 2.4 Lane Configuration
    • 2.5 PCIe/XAUI Fabric SPLL Configuration
    • 2.6 Signal Integrity Options
    • 2.7 Transmit De-Emphasis
    • 2.8 Receive CTL Equalization
    • 2.9 Power Down Register Settings
    • 2.10 High Speed Serial Interface Control Registers
      • 2.10.1 High Speed Serial Interface Registers Configuration
    • 2.11 Firmware (SmartFusion2 Only)
    • 2.12 Simulation Level
    • 2.13 High Speed Serial Interface Configuration Path - SmartFusion2
    • 2.14 High Speed Serial Interface Configuration Path - IGLOO2 Initialization
  • 3 Port Description
  • 4 Revision History
  • Microchip FPGA Support
  • The Microchip Website
  • Product Change Notification Service
  • Customer Support
  • Microchip Devices Code Protection Feature
  • Legal Notice
  • Trademarks
  • Quality Management System
  • Worldwide Sales and Service

2.10 High Speed Serial Interface Control Registers

The High Speed Serial Interface has a set of registers that can be configured at run time. The configuration values for these registers represent different parameters, for example, AXI BAR Window. For details about these registers, see the UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces User Guide.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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