3.4 PCIe AXI Slave Ports
The following table lists the various PCIe AXI slave ports.
Ports | Direction | Port Group |
---|---|---|
AXI_S_AWID[3:0] | IN | AXI_SLAVE |
AXI_S_AWADDR[31:0] | IN | |
AXI_S_AWLEN[3:0] | IN | |
AXI_S_AWSIZE[1:0] | IN | |
AXI_S_AWBURST[1:0] | IN | |
AXI_S_AWVALID | IN | |
AXI_S_AWREADY | OUT | |
AXI_S_AWLOCK[1:0] | IN | |
AXI_S_WID[3:0] | IN | |
AXI_S_WSTRB[7:0] | IN | |
AXI_S_WLAST | IN | |
AXI_S_WVALID | IN | |
AXI_S_WDATA [63:0] | IN | |
AXI_S_WREADY | OUT | |
AXI_S_BID[3:0] | OUT | |
AXI_S_BRESP[1:0] | OUT | |
AXI_S_BVALID | OUT | |
AXI_S_BREADY | IN | |
AXI_S_ARID[3:0] | IN | |
AXI_S_ARADDR[31:0] | IN | |
AXI_S_ARLEN[3:0] | IN | |
AXI_S_ARSIZE[1:0] | IN | |
AXI_S_ARBURST[1:0] | IN | |
AXI_S_ARVALID | IN | |
AXI_S_ARLOCK[1:0] | IN | |
AXI_S_ARREADY | OUT | |
AXI_S_RID[3:0] | OUT | |
AXI_S_RDATA[63:0] | OUT | |
AXI_S_RRESP[1:0] | OUT | |
AXI_S_RLAST | OUT | |
AXI_S_RVALID | OUT | |
AXI_S_RREADY | IN |