3.3 PCIe AXI Master Ports
The following table lists the various PCIe AXI master ports.
Ports | Direction | Port Group |
---|---|---|
AXI_M_AWID[3:0] | OUT | AXI_MASTER |
AXI_M_AWADDR[31:0] | OUT | |
AXI_M_AWLEN[3:0] | OUT | |
AXI_M_AWSIZE[1:0] | OUT | |
AXI_M_AWSIZE[1:0] | OUT | |
AXI_M_AWVALID | OUT | |
AXI_M_AWREADY | IN | |
AXI_M_WID[3:0] | OUT | |
AXI_M_WSTRB[7:0] | OUT | |
AXI_M_WLAST | OUT | |
AXI_M_WVALID | OUT | |
AXI_M_WDATA[63:0] | OUT | |
AXI_M_WREADY | IN | |
AXI_M_BID[3:0] | IN | |
AXI_M_BRESP[1:0] | IN | |
AXI_M_BVALID | IN | |
AXI_M_BREADY | OUT | |
AXI_M_ARID[3:0] | OUT | |
AXI_M_ARADDR[31:0] | OUT | |
AXI_M_ARLEN[3:0] | OUT | |
AXI_M_ARSIZE[1:0] | OUT | |
AXI_M_ARBURST[1:0] | OUT | |
AXI_M_ARVALID | OUT | |
AXI_M_ARREADY | IN | |
AXI_M_RID[3:0] | IN | |
AXI_M_RDATA[63:0] | IN | |
AXI_M_RRESP[1:0] | IN | |
AXI_M_RLAST | IN | |
AXI_M_RVALID | IN | |
AXI_M_RREADY | OUT |