Libero® SoC v2021.2

3.2 PCIe Ports

The following table lists the various PCIe ports.

Table 3-2. PCIe Ports
Ports	Direction
CORE_RESET_N	IN
PHY_RESET_N	IN
CLK_BASE	IN
PCIE_INTERRUPT[3:0]	IN
PCIE_SYSTEM_INT	OUT
SPLL_LOCK	OUT
PLL_LOCK_INT	OUT
PLL_LOCKLOST_INT	OUT
PCIE_EV_1US	OUT
PCIE_WAKE_N	OUT
PCIE_WAKE_REQ	IN
PCIE_PERST_N	IN
REFCLK<x>_OUT where x can be 0 or 1 depending on whether REFCLK0 or REFCLK1 is selected as the Reference Clock Source.	OUT

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