3.9 PAD Ports
The following table lists the various PAD ports.
| Ports | Direction | Ports Group | Description |
|---|---|---|---|
| REFCLK<x>_SE | IN | PADs_IN | Where x can be 0 or 1, depending on whether REFCLK0 (Single-ended) or REFCLK1 (Single-ended) is selected as the Reference Clock Source. |
| RXD0_P, RXD0_N | IN | Differential input pair for lane 0 (Rx data). | |
| RXD1_P, RXD1_N | IN | Differential input pair for lane 1 (Rx data). | |
| RXD2_P, RXD2_N | IN | Differential input pair for lane 2 (Rx data). | |
| RXD3_P, RXD3_N | IN | Differential input pair for lane 3 (Rx data). | |
| REFCLK<x>_P, REFCLK<x>_N | IN | Differential input reference clock pair. These port names can be REFCLK0 or REFCLK1, depending on your selection (see Figure 1-1). | |
| TXD0_P, TXD0_N | OUT | PADs_OUT | Differential output pair for lane 0 (Tx data) |
| TXD1_P, TXD1_N | OUT | Differential output pair for lane 1 (Tx data) | |
| TXD2_P, TXD2_N | OUT | Differential output pair for lane 2 (Tx data) | |
| TXD3_P, TXD3_N | OUT | Differential output pair for lane 3 (Tx data) |