3.8 EPCS Ports per Lane
The following table lists the various EPCS ports per lane.
| Ports | Direction | Ports Group |
|---|---|---|
| EPCS_<n>_PWRDN | IN | EPCS_<n>_IN Where n can be 0, 1, 2 or 3 depending on the number of configured lanes. |
| EPCS_<n>_TX_VAL | IN | |
| EPCS_<n>_TX_OOB | IN | |
| EPCS_<n>_RX_ERR | IN | |
| EPCS_<n>_RESET_N | IN | |
| EPCS_<n>_TX_DATA[<wd>:0] | IN | |
| EPCS_FAB_REF_CLK When Fabric is selected as the Reference Clock Source in the Configurator | IN | |
| EPCS_<n>_READY | OUT | EPCS_<n>_OUT Where n can be 0, 1, 2 or 3 depending on the number of configured lanes. |
| EPCS_<n>_TX_CLK_STABLE | OUT | |
| EPCS_<n>_TX_CLK | OUT | |
| EPCS_<n>_RX_CLK | OUT | |
| EPCS_<n>_RX_VAL | OUT | |
| EPCS_<n>_RX_IDLE | OUT | |
| EPCS_<n>_TX_RESET_N | OUT | |
| EPCS_<n>_RX_RESET_N | OUT | |
| EPCS_<n>_RX_DATA[19:0] | OUT | |
| REFCLK<x>_OUT Where x can be 0 or 1 depending on whether REFCLK0 or REFCLK1 is selected as the Reference Clock | OUT |
Note: <n>: indicates the lane on which EPCS is configured.
Note: <wd>: valid values are 19,15, 9, 7, 4, and 3.