4.1 Designer Documentation Catalog

The following table describes the user guides that compose the Designer Documentation Catalog. The right column provides information about using Designer for design implementation. Use Designer and its components to import files, compile, layout, and run the floorplanning, timing, and power analysis tools.

Table 4-1. Designer User Guides
Designer User Guide	Description
MultiView Navigator User’s Guide	This guide includes documentation for ChipPlanner, PinEditor, I/O Attribute Editor, and NetlistViewer in MultiView Navigator (MVN). It provides information about: Placing macros, floorplanning, and viewing chip resources Using NetlistViewer in the MVN to view your netlist Using the Pin Editor in MVN Using the I/O Attribute Editor tool
Design Constraints User Guide	Provides a complete reference for creating and modifying timing, physical, and netlist optimization constraints in Libero IDE, including families and file formats supported for each constraint. It also describes how to create and modify I/O constraints with the I/O Attribute Editor, before compiling your design.
SmartPower User Guide	Describes how to use SmartPower for power analysis.
SmartTime User Guide	Describes how to use SmartTime for timing analysis and how to set clock constraints.
Timer User’s Guide	Provides a detailed description of how to use Timer for timing analysis of designs created for SX, MX, 3200DX, ACT3, ACT2, and ACT1 families.
ChipEditor User’s Guide	Provides a detailed description of how to use Chip Editor to place macros in designs created for SX, MX, 3200DX, ACT3, ACT2, and ACT1 families.
NetlistViewer (non-MVN) User Guide	Contains information about using non-MVN version of NetlistViewer to view nets, ports, and instances and to trace signals in designs created for SX, MX, 3200DX, ACT3, ACT2, and ACT1 families.
PinEditor (non-MVN) User Guide	Describes how to use the non-MVN version of PinEditor to assign I/O ports to package pins in designs created for SX, MX, 3200DX, ACT3, ACT2, and ACT1 families.
SmartGen Cores Reference Guide	Provides descriptions of cores that can be generated using the SmartGen Core Builder software.
Analog System Builder, FlashROM and Flash Memory System Builder User Guide	Describes how to use the FlashROM generator, Analog System Builder, and Flash Memory System Builder.
Microchip HDL Coding Style Guide	Provides preferred coding styles for the Microchip architecture and information about optimizing your HDL code for Microchip devices.
Innoveda® eProduct Designer Interface Guide - Windows	Contains information to assist in the design of Microchip devices using eProduct Designer and the Designer Series software on Windows machines.
VHDL VITAL Simulation Guide Libero SoC	Contains information to assist in simulating Microchip designs using a Vital-compliant VHDL simulator.
Verilog Simulation Guide	Contains information to assist in simulating Microchip designs using a Verilog simulator.
Silicon Explorer II User’s Guide	Contains information about how to use Silicon Explorer II, our integrated verification and logic analysis tool for Windows. Silicon Explorer II is not available on UNIX.
FlashPro User Guide	Contains information about how to program Microchip ProASIC® and ProASIC PLUS® devices using the FlashPro software and device programmer. FlashPro is not available on UNIX.
Silicon Sculptor User’s Guide	Contains information about using Silicon Sculptor to program your Microchip device. Silicon Sculptor is not available on UNIX.
Antifuse Macro Library Guide	Provides descriptions of Microchip library elements for Microchip antifuse device families (including Axcelerator). Symbols, truth tables, and module count are included for all macros.
ProASIC and ProASIC PLUS Macro Library Guide	Provides descriptions of Microchip library elements for Microchip ProASIC and ProASIC PLUS device families. Symbols, truth tables, and module counts are included for all the ProASIC and ProASIC PLUS macros.
IGLOO, ProASIC3, and Fusion Macro Library Guide	Provides descriptions of Microchip library elements for Microchip Fusion®, ProASIC3, and ProASIC3E device families. Symbols, truth tables, and module counts are included for all the Fusion and ProASIC3/E macros.
ChainBuilder User’s Guide v1.1	Allows you to pass through non-Flash devices to program APA device(s) in series and the ability to program multiple APA devices concurrently. ChainBuilder is not available on UNIX.