4.3.4 SDRAM
SAM V71 Xplained Ultra features one external IS42S16100E-7BLI, 512Kx16x2, 144MHz, SDRAM. The SDRAM is connected to chip select NCS1. SDRAM access can be configured in the SDRAM Controller in the SAM V71. Table 4-23 lists all I/O-lines connected to the SDRAM.
Due to the maximum communication speed of 144MHz in the on-board SDRAM and stubs created by the routing to the LCD connector (EXT4), the SDRAM is accessible up to 133MHz with the GPIO configured in low-drive mode. With GPIO configured as high drive or with a cable connected to the LCD connector the maximum communication speed is lowered further. See EBI Signal Integrity for more information.
| SAM V71 pin | Function | SDRAM function | Shared functionality |
|---|---|---|---|
| PC00 | D0 | Data line 0 | LCD |
| PC01 | D1 | Data line 1 | LCD |
| PC02 | D2 | Data line 2 | LCD |
| PC03 | D3 | Data line 3 | LCD |
| PC04 | D4 | Data line 4 | LCD |
| PC05 | D5 | Data line 5 | LCD |
| PC06 | D6 | Data line 6 | LCD |
| PC07 | D7 | Data line 7 | LCD |
| PE00 | D8 | Data line 8 | LCD and Shield |
| PE01 | D9 | Data line 9 | LCD |
| PE02 | D10 | Data line 10 | LCD |
| PE03 | D11 | Data line 11 | LCD and Shield |
| PE04 | D12 | Data line 12 | LCD and Shield |
| PE05 | D13 | Data line 13 | LCD and Shield |
| PA15 | D14 | Data line 14 | LCD |
| PA16 | D15 | Data line 15 | LCD |
| PC20 | A2 | Address line 0 | |
| PC21 | A3 | Address line 1 | |
| PC22 | A4 | Address line 2 | |
| PC23 | A5 | Address line 3 | |
| PC24 | A6 | Address line 4 | |
| PC25 | A7 | Address line 5 | |
| PC26 | A8 | Address line 6 | |
| PC27 | A9 | Address line 7 | |
| PC28 | A10 | Address line 8 | |
| PC29 | A11 | Address line 9 | |
| PD13 | SDA10 | Address line 10 | |
| PA20 | BA0 | Bank select line 0 | |
| PD23 | SDCK | Clock | |
| PD14 | SDCKE | Clock Enable | |
| PC15 | SDCS | Chip Select | |
| PD16 | RAS | RAS | Shield |
| PD17 | CAS | CAS | |
| PD29 | SDWE | Write Enable | |
| PC18 | A0/NBS0 | LDQM | |
| PD15 | NWR1/NBS1 | UDQM | Shield |