1.4 SPI Timing
The SPI has four modes of operation, 0 through 3. These modes essentially control the way data is clocked in or out of an SPI device. The configuration is done by two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA) control bit selects one of the two fundamentally different transfer formats. To ensure a proper communication between master and slave both devices have to run in the same mode. This might require a reconfiguration of the master to match the requirements of different peripheral slaves.
| SPI mode | CPOL | CPHA | Shift SCK-Edge | Capture SCK-Edge |
|---|---|---|---|---|
| 0 | 0 | 0 | Falling | Rising |
| 1 | 0 | 1 | Rising | Falling |
| 2 | 1 | 0 | Rising | Falling |
| 3 | 1 | 1 | Falling | Rising |
The clock polarity has no significant effect on the transfer format. Switching this bit causes the clock signal to be inverted (active high becomes active low and idle low becomes idle high). The settings of the clock phase, however, selects one of the two different transfer timings. Since the MOSI and MISO lines of the master and the slave are directly connected to each other, the diagrams show the timing of both devices, master and slave. The SS line is the slave select input of the slave. The SS pin of the master is not shown in the diagrams. It has to be inactive by a high level on this pin (if configured as input pin) or by configuring it as an output pin.