2.2.1 System Initialization Overview

The following figure shows the system initialization flow, consisting of hardware and firmware initialization, after power-on.
Figure 2-4. System Initialization

After connecting the supply voltage to the VS pin, the ATA8510/15 always starts in OFFMode. All internal circuits are disconnected from the power supply. The ATA8510/15 can be woken up by one of the following power-on reset (POR) events:

  • Setting the PWRON pin to HIGH
  • Setting one of the NPWRON1..6 pins to LOW

For more information on the OFFMode, refer to OFFMode. A POR enables the DVCC regulator. The FRC oscillator starts when the DVCC voltage reaches the operating voltage. At the same time, the internal AVR reset is triggered. After reaching stable operating conditions, the FRC provides the clock for the hardware initialization state machine. The initialization state machine reads the fuses and resets the SRAM content to “0x00”. The internal AVR reset is released when the hardware initialization is done. The system is now controlled by the firmware.

The firmware steps through the following tasks:

  • Check for a correct wake-up condition. This is done by reading the pin registers (PINB and PINC) to identify the wake-up source. If a correct wake-up is detected, the wake-up source is signaled as an event. If no wake-up source is detected, the wake-up is considered invalid and the ATA8510/15 switches back to OFFMode. Reset sources like watchdog reset, external reset or brown-out reset are not checked. This implies that the chip goes to OFFMode if, for example, a watchdog reset occurred and no (N) PWRON pin was triggered.
  • Disable the watchdog timer
  • Firmware initialization: The system is initialized according to the EEPROM settings, see Firmware Initialization.

If the firmware initialization is done successfully, the system enters the selected operating mode after the system start; otherwise the firmware disables the watchdog timer, sets the SYS_ERR flag and stays in an endless loop. SPI communication is still possible in this case, such as to program the EEPROM or read out the error code from the SRAM (see Error Codes for details).

The operating mode after the system start is selectable by the EEPROM variable eepTrxConfig.sysStartConfig.OPM[1:0]:

  • IDLEMode
  • TXMode
  • RXMode
  • PollingMode

In the variables eepTrxConfig.sysStartConfig and eepTrxConfig.sysStartSvcChConfig, various options can be configured, which are addressed during the start-up operating mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0019 sysStartConfig RF_CAL ANT_TUNE VCO_TUNE IDLEModeSelector — TMDEN OPM[1:0]
0x001A sysStartSvcChConfig enaPathB enaPathA Ch[1:0] — Ser[2:0]

The following table shows which options are relevant for which operating mode.

Table 2-1. Operating Mode Options
OPM RF_CALANT_TUNEVCO_TUNEIDLEMode SelectorTMDENenaPathBenaPathACh[1:0]Ser[2:0]
IDLEMode — — — x — — — — —
TxMode x x x x x x x x x
RxMode x — x x x x x x x
PollingMode — — x x x — — — x(1)
Note: If PollingMode is selected, bits 0 to 3 of eepTrxConfig.sysStartSvcChConfig define the start index of the polling array.

For more details, see sEEPromTrxConfig eepTrxConf. A description of the various operating modes can be found in Operating Modes Overview.