2.12.4 sEEPromTrxConfig eepTrxConf

The sEEPromTrxConfig eepTrxConf variable contains the general transceiver configurations.

clkConfig

The clkConfig variable contains the clock configuration. See Clock Initialization for a functional description, and System Clock and Clock Options for a hardware description.

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: SRCAO – SRC Always On

0 = SRC “always on” disabled

1 = SRC “always on” enabled

This bit is copied to the corresponding bit in the CMOCR hardware register.

Bit 4: FRCAO – FRC Always On

0 = FRC “always on” disabled

1 = FRC “always on” enabled

This bit is copied to the corresponding bit in the CMOCR hardware register.

Bit 3: Reserved Bits

This bit is reserved for future use and must be set to ‘0’.

Bit 2: CLKOEN – Clock Output Driver Enable to CLK_OUT

0 = Clock output driver disabled

1 = Clock output driver enabled

This bit is copied to the corresponding bit in the CLKOCR hardware register.

Bits 1..0: CLKOS[1:0] – Clock Output Select

These bits are copied to the corresponding bits in the CLKOCR hardware register.

spiConfig

The spiConfig variable contains the SPI configuration. The settings are copied to the corresponding bits of the SPCR hardware register. See SPI Initialization for a functional description, and SPI – Serial Peripheral Interface for a hardware description.

Bit 7: DORD – Data Order

0 = MSB of the data word is transmitted first

1 = LSB of the data word is transmitted first

Bit 6: CPOL – Clock Polarity

When this bit is written to ‘1’, SCK is HIGH when idle. When CPOL is written to ‘0’, SCK is LOW when idle.

Bit 5: CPHA – Clock Phase

The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK.

Bits 4..0: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

sysConfig

The sysConfig variable contains power supply and interrupt settings. See Power Supply Settings and FIFO Interrupt Initialization for a functional description. The hardware descriptions can be found in Power Management and Data and Support FIFOs.

Bits 7..6: Reserved Bits

These bits are reserved for future use and must be set to ‘0’.

Bit 5: VS22V – VS Power Amplifier 2.2V (only activated if VS5V = 1)

0 = VS power amplifier 3V

1 = VS power amplifier 2.2V

Bit 4: VS5V – Power Supply internal LDO

0 = 3V power supply – Directly supply PA via pin 8/VS_PA

1 = 5V power supply – Supply PA via pin 13/VS, internal LDO activated

Bit 3: SFIFO_OFL_UFL_RX_disable – Support FIFO Overflow Underflow RX Interrupt Disable

0 = SFIFO overflow/underflow RX interrupt enabled

1 = SFIFO overflow/underflow RX interrupt disabled

Bit 2: DFIFO_OFL_UFL_RX_disable – Data FIFO Overflow Underflow RX Interrupt Disable

0 = DFIFO overflow/underflow RX interrupt enabled

1 = DFIFO overflow/underflow RX interrupt disabled

Bit 1: AVCCdisable – AVCC Low Disable

0 = AVCCLOW enabled

1 = AVCCLOW disabled

Bit 0: LOWBATTdisable – Low Battery Disable

0 = LOWBATT enabled

1 = LOWBATT disabled

clkOutDiv

The clkOutDiv variable is a copy of the clock output divider register (CLKOD) and contains the output clock divider configuration. CLKOD must be multiplied by 2 to get the actual divider value. See Clock Initialization for a functional description, and System Clock and Clock Options for a hardware description.

Bits 7..0: CLKOD[7:0] – Clock Output Divider

sysStartConfig

The sysStartConfig variable contains the system mode configuration for the operating mode entered after system initialization. Tune and check functions are not performed when IDLEMode is selected as OPM. Table 2-1 shows which options are available for the selected operation mode.

Bit 7: RF_CAL – RF Calibration at System Start

0 = RF calibration at system start disabled

1 = RF calibration at system start enabled

Bit 6: ANT_TUNE – Antenna Tuning at System Start

0 = Antenna tuning at system start disabled

1 = Antenna tuning at system start enabled

Bit 5: VCO_TUNE – VCO Tuning at System Start

0 = VCO tuning at system start disabled

1 = VCO tuning at system start enabled

Bit 4: IDLEModeSelector – IDLEMode Selector

0 = IDLEMode(RC) selected

1 = IDLEMode(XTO) selected

Bit 3: Reserved Bit

This bit is reserved for future use and must be set to ‘0’.

Bit 2: TMDEN – Transparent Mode Data Enable

0 = Buffered mode is enabled

1 = Transparent mode is enabled

Bits 1..0: OPM[1:0] – Operating Mode after System Init

sysStartSvcChConfig

The sysStartSvcChConfig variable contains the service/channel configuration for the operating mode that is entered after system initialization.

Bit 7: enaPathB – Enable Path B

0 = Path B disabled

1 = Path B enabled

Bit 6: enaPathA – Enable Path A

0 = Path A disabled

1 = Path A enabled

Bits 5..4: Ch[1:0] – Channel[1:0]

Bit 3: Reserved Bits

This bit is reserved for future use and must be set to ‘0’.

Bits 2..0: Ser[2:0] – Service[2:0]

svcInitConf

The svcInitConf variable contains the SRAM service initialization configuration. See SRAM Service Initialization for a functional description.

Bit 7: UpdateSvc4 – Update Flag Service 4

0 = Service 4 (SRAM) is not initialized

1 = Service 4 (SRAM) is initialized

Bits 6..5: eepSvc[1:0] – EEPROM Service Identifier

Number of EEPROM service that is used for initialization of service 4 (SRAM)

Bit 4: 1 – must always be ‘1’

Bit 3: UpdateSvc3 – Update Flag Service 3

0 = Service 3 (SRAM) is not initialized

1 = Service 3 (SRAM) is initialized

Bits 2..1: eepSvc[1:0] – EEPROM Service Identifier

Number of EEPROM service that is used for initialization of service 3 (SRAM)

Bit 0: 0 – must always be ‘0’